1. Field of the Invention
The present invention relates to integrated circuits of the type having a system bus to which a processor is connectable and a peripheral bus to which one or more peripheral units are connected.
2. Description of the Prior Art
It is known to provide an integrated circuit with a system bus to be used for high performance system modules, and a peripheral bus to be used for low power peripheral devices. The system modules, such as a processor, a Direct Memory Access (DMA) controller, etc may typically be provided as part of the integrated circuit, but alternatively one or more of such system modules may be provided off-chip. Similarly, the peripheral devices that connect to the peripheral bus may be provided within the integrated circuit, or alternatively may be provided off-chip. However, for the peripheral devices that are provided off-chip, there will typically be provided some corresponding on-chip logic that is connected to the peripheral bus, and is used to interface with the peripheral device. Hence, for the purpose of the present description, the term "peripheral unit" will be used to refer to the logic provided within the integrated circuit and connected to the peripheral bus, irrespective of whether that logic is actually the peripheral device itself, or a piece of interface logic used to interface with a peripheral device provided off-chip.
The system bus is typically a high performance bus, which supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low power peripheral macrocell functions. The peripheral bus, on the other hand, is a low power bus, arranged to reduce power consumption and interface complexity to support peripheral functions. It enables multiple peripheral units to be connected without loading the main system bus, which would adversely affect the operation of the system bus. Typically, the system bus and peripheral bus operate at the same clock speed, and any clock resynchronisation required due to the particular operating speed of a peripheral unit is performed at that peripheral unit.
When developing integrated circuits, the issue of power consumption is very important. It is becoming more commonplace for such integrated circuits to be used in products which operate from battery power, such as portable laptop computers, mobile phones, personal organizers, etc. In such situations, it is clearly desirable to reduce the power consumption of the integrated circuits as much as possible, in order to improve the battery life of the products, i.e. the amount of time the products can be used for before needing to replace or recharge the batteries. However, it should be noted that it is not just in the area of battery powered products where power consumption is a concern, and there is generally a desire to reduce power consumption wherever possible. For example, by reducing power consumption, it is also possible to reduce heat generation, and hence reduce the need for heat dissipating elements such as fans and heat sinks to be provided, thereby reducing cost and size.
Although the provision of a peripheral bus enables the power consumption of the integrated circuit to be reduced, the actual reduction in power consumption is dependent on the number of peripheral units connected to the peripheral bus. Increasingly, there is a need for such integrated circuits to support more and more peripheral units, and the more peripheral units connected to the peripheral bus, the higher the capacitance of the peripheral bus. Since the power consumption of the peripheral bus is proportional to the capacitance of the bus, it is clear that the power consumption of the peripheral bus increases as more and more peripheral units are connected to it, and hence the overall power savings of the integrated circuit are reduced.
Accordingly, it is an object of the present invention to provide a technique which enables power consumption to be reduced with respect to the power consumption of such prior art integrated circuits.